Article ID: 000094962 Content Type: Error Messages Last Reviewed: 05/18/2023

Why does the Intel Agilex® FPGA EMIF fail timing when Traffic Generator and ECC are enabled in Intel® Quartus® Prime Pro Edition Software version 20.3?

Environment

  • Intel® Quartus® Prime Design Software
  • External Memory Interfaces Debug Component Intel® FPGA IP
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    Description

     Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3, you may encounter timing failures in the Intel Agilex® FPGA DDR4 IP when Traffic Generator and ECC are both enabled.

     

     

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3 onwards.

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