Due to a problem in the Intel® Quartus® Prime Pro Edition Software v23.1, when using both the PCIe PHY and non-PCIe PHY with PMA clocking mode on the same F-tile on Intel Agilex® 7 devices, you might see the following support logic generation error:
Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings
Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on the current device.
This error will not happen if an additional non-PCIe PHY with system PLL clocking mode is used and a system PLL for the non-PCIe PHY with system PLL clocking mode has been enabled.
This error occurs when a system PLL has not been enabled for the configuration of non-PCIe PHYs.
To work around this problem, enable system PLL #0 for configuration of PMA direct PHY with PMA clocking mode, and leave the output clock of the system PLL #0 unconnected. You must use system PLL #0, not system PLL #1 or #2 for the workaround. System PLL #1 or #2 should be used for the PCIe Intel FPGA IP.