Article ID: 000094895 Content Type: Troubleshooting Last Reviewed: 11/30/2023

Why does the E-tile CPRI PHY Intel® FPGA IP have an unconstrained clock *|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 or earlier,  there is an unconstrained clock in the E-tile CPRI PHY Intel® FPGA IP as follows:

    *|alt_cpriphy_c3_0|SL_SOFT_I[0].sl_soft|latency_measure_inst|am_muxsel_gen_inst|async_out

    Resolution

    This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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