Article ID: 000094887 Content Type: Troubleshooting Last Reviewed: 12/07/2024

Why is the o_rx_pcs_ready of the F-Tile Ethernet FPGA IP not asserted in PAM4 cases with PMA REFCLK set as 312.5MHz variants fail with PCS ready low when VSR assignment is enabled in the design QSF ?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, the o_rx_pcs_ready of the F-Tile Ethernet IP is not asserted in PAM4 cases with PMA REFCLK set as 312.5MHz variants fail with PCS ready low when VSR assignment is enabled in the design QSF.

    Resolution

    To work around this problem, disable the VSR assignment in the design QSF.
    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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