Article ID: 000094750 Content Type: Troubleshooting Last Reviewed: 05/30/2023

What is a possible cause of the external hardware access error of PMBUS when the error is observed during Avalon® streaming x8 configuration?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The possible root cause is a signal integrity problem on PMBUS if the external hardware access error of PMBUS is observed during Avalon® streaming x8 configuration, but not observed during JTAG configuration.

    You can use the Device Information of the Configuration Debugger tool to know what configuration error occurs.  When an external hardware access error occurs, the Device Information  displays as follows:

    Major Error Code: 0x0000F002
    Major Error Type: ERR_EX_HW_ACCESS_FAIL

    Error Message:
    Error message received from device: External hardware access error.
    Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Intel Quartus  Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board.

    PMBUS uses a bidirectional open-drain buffer for each port in both the host device and the regulator device.  The low state is actively driven by the host or the regulator device. However, the high state is passively provided through the pull-up resistor when all the buffers on the signal are tri-stated.  Because of the nature of PMBUS, the high state is relatively vulnerable to noise toward to low.  

    If the hardware access error is observed during Avalon streaming x8 configuration, but not observed during JTAG configuration, any signal of Avalon streaming x8 configuration may cause noise on PMBUS and affects the PMBUS operation.

    Resolution

    To improve noise from the Avalon streaming x8 configuration signals to PMBUS signals, consider the following ways:

    1. Lower drive strength of Avalon streaming x8 configuration signals from the configuration host. 
    2. Reduce the resistance of pull-the up resistor on PMBUS signals.
    3. Change the board layout to reduce cross-talk between Avalon streaming x8 configuration signals and PMBUS signals.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs