Article ID: 000094700 Content Type: Troubleshooting Last Reviewed: 05/09/2023

Why does H2F interface data width in simulation file not match the data width set in HPS IP in the Platform Designer for Intel Agilex® 7 ​device?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, when you set H2F data width to 128 bit in HPS IP for Intel Agilex® 7 ​device in the Platform Designer and generate the system, you will find the S2F_DATA_WIDTH is set to wrong value (0) in the generated simulation file.

     

    Resolution

    The problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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