You will see the fitter error "Error(14566): The Fitter cannot place <amount> periphery component(s) due to conflicts with existing constraints (<amount> LVDS_CHANNEL(s))" when trying to compile a design with TX LVDS SERDES that cover multiple banks.
The error is seen if the channels are not put on the same bank as the PLL, as the first one is mapped to the SERDES IP block. For example, the pins are assigned to banks 3B, 3C, and 3D, with the reference clock for the PLL assigned to a CLK pin on bank 3C.
The arrangement is as below:
3A: tx_data[0..15]
3B: tx_data[16..38]
3C: tx_data[39..51]
Please contact your local Application Engineer to get the workaround for this issue and quote Bug ID: 15012251590.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.