Article ID: 000094603 Content Type: Troubleshooting Last Reviewed: 08/02/2023

Why is the F2SDRAM bridge unstable, or unable to perform read/write transactions after performing a core.rbf full configuration through FPGA overlay in Linux?

Environment

u-boot-socfpga

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the bridge driver for the F2SDRAM bridge the following  behaviour may be seen: 

- A  lockup condition in the F2SDRAM bridge when

  • You perform a full FPGA core configuration in Linux through an FPGA overlay.
  • You disable the bridge in the U-Boot console after a core.rbf configuration by running the “disable bridge” command.

- A Linux kernel exception  (data abort) or a non-completed F2SDRAM transaction after FPGA Core Re-Configuration

  • You perform a full FPGA core configuration in Linux through an FPGA overlay
  • An Arm AXI Controller issues transactions to the HPS via the F2SDRAM bridge
  • You perform a full FPGA core re-configuration in Linux through an FPGA overlay
  • An Arm AXI Controller issues transactions to the HPS via the F2SDRAM bridge
  • Linux Kernel Exception  : Null Pointer Exception maybe seen,  or the Arm AMBA AXI Ready signsl from the FPGA2SDRAM bridge may go inactive before the first transaction completes

These problem does not affect the H2F or Lightweight H2F bridge.

 

These problem impacts Intel Agilex® 7 SoC,  Intel® Stratix® 10 FPGA and Intel® eASIC™ N5X devices.

 

 

Resolution

The problem has been fixed with the latest GitHub arm-trusted-firmware version socfpga_v2.7.1 and v2.8.0 and U-Boot version socfpga_v2022.10.

 

For the ATF flow, the patch is available in the arm-trusted-firmware version socfpga_v2.7.1 and v2.8.0 - https://github.com/altera-opensource/arm-trusted-firmware

Patch commit ID:

 

For legacy (Non-ATF) flow – the patch is available in u-boot-socfpga - socfpga_v2022.10 - https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2022.10

Patch commit ID:

 

Alternatively, you may use the following approach to avoid the F2SDRAM bridge lockup problem:

    • Avoid using the FPGA overlay for full configuration.
    • Do not perform a bridge disable in the U-Boot stage.

 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs