Article ID: 000094551 Content Type: Errata Last Reviewed: 08/15/2023

Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the packet counters within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will roll over when small back-to-back packets are encountered, and the packet counters are nearing the saturated value (i.e., all F’s). 

    Resolution

    There is no workaround for this problem. 
    This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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