Article ID: 000094483 Content Type: Troubleshooting Last Reviewed: 06/17/2023

Why does Triple-Speed Ethernet Intel® FPGA IP fail for 10M/100M speeds when MAC is configured for 8-bit FIFO?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Triple-Speed Ethernet Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to problem in the transmitter of the Triple-Speed Ethernet Intel® FPGA IP and the F-Tile Triple-Speed Ethernet Intel® FPGA IP, the design fails when the MAC only variant is configured for an 8-bit FIFO.

    Resolution

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1.

    Related Products

    This article applies to 11 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Arria® II FPGAs
    Arria® V FPGAs and SoC FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Cyclone® IV FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® MAX® 10 FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Stratix® IV FPGAs
    Stratix® V FPGAs

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