Article ID: 000094227 Content Type: Troubleshooting Last Reviewed: 06/04/2025

Critical Warning (332049): Ignored create_generated_clock at altera_emr_unloader.sdc(14): Argument <targets> is an empty collection

Environment

    Intel® Quartus® Prime Standard Edition
    Error Message Register Unloader Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard Edition Software version 22.1, you might see this critical warning when using the Error Message Register Unloader IP.

You will also see an unconstrained clock reported in the Unconstrained Paths Report in the Timing Analyzer, as shown below, when using the Error Message Register Unloader IP. This is due to the constraint in altera_emr_unloader.sdc, which failed to address this issue.

*|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH

Resolution

To work around this problem in the Quartus® Prime Standard Edition Software version 22.1, follow these steps:

  1. In the altera_emr_unloader.sdc file, comment out line 14. 
  2. Add the create_generated_clock constraint to the altera_emr_unloader.sdc file. For example:

create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_pins {*|alt_fault_injection_component|alt_fi_inst|*oscillator|clkout}] [get_keepers { *|emr_unloader_component|current_state.STATE_CLOCKHIGH}]

This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.

Related Products

This article applies to 3 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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