Article ID: 000094214 Content Type: Troubleshooting Last Reviewed: 10/31/2023

Why don’t I see the “tx_pmaif_fifo_overflow” port on my RTL instance of the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP when using Intel Quartus Prime Pro Edition Software v22.4?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 22.4, the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP erroneously provides an option to enable the “Enable tx_pmaif_fifo_overflow port”.

    Resolution

    There is no workaround for this problem. The “tx_pmaif_fifo_overflow” port should not be enabled in the Intel Agilex® 7 F-tile PMA/FEC Direct Multirate Intel® FPGA IP.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Additional information

    This problem has been fixed starting in version 23.1 of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs