Article ID: 000093986 Content Type: Troubleshooting Last Reviewed: 11/15/2024

Is there a syntax error when using the VHDL file of the ALTMULT_COMPLEX FPGA IP?

Environment

    Intel® Quartus® Prime Standard Edition
    ALTMULT_COMPLEX Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 and earlier, the VHDL file generated for the ALTMULT_COMPLEX FPGA IP, <ip_variation_name>.vhd, contains syntax errors.

Using the generated IP files in the VHDL language is impossible.

 

 

Resolution

As a workaround, the user should generate the IP in Verilog HDL language.

 

Related Products

This article applies to 7 products

Intel® Cyclone® 10 LP FPGA
Intel® MAX® 10 FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs

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