Why do I get an error when simulating the R-Tile Multi Channel DMA Intel® FPGA IP for PCI Express Design Example for Intel® Agilex™ devices using VCS simulator?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, an error will be observed when trying to simulate the R-Tile Multi Channel DMA Intel® FPGA IP for PCI Express design example using VCS simulator.

The error informaiton below will be seen:                                                                  

INFO:          497636 ns Starting DMA Read....H2D                                                                            

INFO:          500949 ns Queue Reset...done                                                                                  

INFO:          501149 ns Waiting for MSI-X Writeback for Read DMA........                                                    

FATAL:        4000000 ns Simulation stopped due to inactivity!                                                               

                                 FAILURE: Simulation stopped due to Fatal error!

FAILURE: Simulation stopped due to error!

$finish called from file "./../..//../../ip/pcie_ed_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/altpcietb_g3bfm_log.v", line 144.

No work around to this problem exists.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.