Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see this internal error in the Platform Designer during HDL generation. This error occurs because the output enable signal is included in the Avalon® Memory Mapped Agent interface of the Generic Component.
Resolution
To work around this problem, remove the output enable signal from the Avalon® Memory Mapped Agent interface of the Generic Component before HDL generation.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.1.