Why do I see Logic Generation Errors when using the F-Tile PMA/FEC Direct PHY Intel Agilex® 7 FPGA IP configured in SDI mode after upgrading from Intel® Quartus® Prime Pro Edition Software v22.3 to v22.4 and later?

You might see Logic Generation Errors when using the F-Tile PMA/FEC Direct PHY Intel Agilex® 7 FPGA IP configured in SDI mode after upgrading from Intel® Quartus® Prime Pro Edition Software v22.3 to v22.4 and later if you have not added "tx_pll_bw_sel” Quartus Settings File (QSF) constraints.

Intel F-Tile transceivers in SDI mode require an additional QSF constraint in Intel Quartus software v21.4 and later. You might see a Logic Generation Error similar to the following in your F-Tile PMA/FEC Direct Intel® FPGA PHY IP in SDI mode, design.

Error example:

Error(21843): Input variables: 

Error(21843): user.bb_f_ux_tx[0] -> du_inst|sdi_mr_du_sys_inst|tx_phy|tx_phy|dphy_hip_inst|persystem[0].perxcvr[0].fgt.tx_ux.x_bb_f_ux_tx

Error(21843): is_used == TRUE

Error(21843): location == UX15

Error(21843): tx_line_rate_bps == 11880000000

Error(21843): tx_pll_bw_sel == TX_PLL_BW_SEL_LOW

Error(21843): tx_tuning_hint == TX_TUNING_HINT_SDI

Error(21843): user.bb_f_ux_rx[0] -> du_inst|sdi_mr_du_sys_inst|rx_phy|rx_phy|U_base_profile|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx

Error(21843): is_used == TRUE

Error(21843): location == UX15

Error(21843): txrx_channel_operation == TXRX_CHANNEL_OPERATION_DUAL_SIMPLEX

To fix this problem, add the following constraint example for each Intel F-Tile transceiver SDI pin.

Constraint example:

set_instance_assignment -name HSSI_PARAMETER "tx_pll_bw_sel=TX_PLL_BW_SEL_MEDIUM" -to <pin_name>

For a full list of all QSF HSSI_PARAMETER assignments required for Intel F-Tile SDI designs, you can generate the SDI II Intel FPGA IP Design Example in the latest version of Intel® Quartus® Prime Pro Edition Software and refer to the QSF file.