Yes, a design with HPS first boot mode is supported to be configured over JTAG on Secure Device Manager (SDM)-based Intel® Stratix® 10 and Intel Agilex® SoC devices.
To generate a HPS first sof file, generate an image intended to be used for a non JTAG configuration mode supported on your board, such as ASx4 or AVST using the Programming File Generator tool in the Intel® Quartus® Prime Software. Ensure the FSBL is added to the input .sof file.
An output .sof file with the name <filename>_hps_auto.sof will be created by the Programming File Generator tool in the chosen output directory. This file contains the FSBL and can be used to configure the SoC FPGA over JTAG.
This is scheduled to be updated in the next release of the Intel Stratix 10 SoC FPGA Boot User Guide and Intel Agilex SoC FPGA Boot User Guide.