Why does the F-Tile Ethernet Intel® FPGA Hard IP design example have recovery timing errors when Deterministic Latency Measurement enabled?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, for the F-Tile Ethernet Intel® FPGA Hard IP, when the Deterministic Latency Measurement option is enabled, and an example design is generated, you might observe recovery timing failure. 

To work around this issue, add the following code into the eth_f_ip.sdc file:

eth_f_constraint_net_delay   *\

                                  *latency_measure_inst|async_pulse_gen_inst|async_pulse* \

                                   2.2ns 1 0 0 0 1

eth_f_constraint_net_delay   *\

                             *latency_measure_inst|async_pulse_gen_inst| cnt[*] \

                             2.2ns 1 0 0 0 1

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

s