Why do I see a restriction on reference clock location with ASIC Proto I/O Standard in PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP?

Due to a problem in Intel® Quartus® Prime Pro Edition Sofware version 22.4, the PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP lanes cannot be shared with the reference clock if the ASIC Proto I/O standard is used.

To work around this problem in Intel® Quartus® Prime Pro Edition Software version 22.4, specify the reference clock location with either Intel® Quartus® Prime Pro Edition Pin Planner or Intel® Quartus® Prime Pro Edition Assignment Editor.

This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.1.