Description
Due to the limitation of the CPRI Intel® FPGA IP core, you might see the error message above if you use more than one CPRI Intel® FPGA IP with RSFEC sharing in the Intel® Stratix® 10 FPGA E-tile and Intel Agilex® 7 FPGA E-tile.
Resolution
To work around this problem, avoid using the CPRI Intel® FPGA IP with RSFEC sharing.
Another workaround is to separately generate and connect the MAC and PHY structure so that the PHY IP can share a single RS-FEC location.
This problem will not be fixed in a future release of the CPRI Intel® FPGA IP core.