Critical Issue
Due to a problem in the Intel® Quartus® Prime Pro Software version 22.3 and earlier, you might see loops being reported for memories that contain read-enable functionality being implemented in MLABs by one of the following reporting methods:
- “Found combinational loop of * nodes” warnings in the Timing Analyzer report.
- “LNT-30011 - Design Contains Combinational Loops” Rule violations in the Design Assistant (Synthesized) report.
- “TMC-20017 - Loops Detected” Rule violations in the Design Assistant (Signoff) report.
- “Loops” reported when running the “check_timing” report in the Timing Analyzer.
- “Node: * was determined to be a clock but was found without an associated clock assignment.” warning in the Timing Analyzer report.
The reported loops result from a latch being implemented on the output of the MLAB to support the read-enable functionality. This latch is not timing analyzed correctly, meaning the functionality cannot be guaranteed in hardware.
This problem may occur for the following memory implementation styles, which are placed in MLAB memory blocks:
- RTL code that directly infers a memory containing read enable functionality.
- Direct memory instantiation, including read enable functionality and a ram_block_type setting of MLAB or AUTO
To work around this problem, do one of the following:
- Avoid the use of read enable functionality.
- For RTL inferred memories, use the ramstyle attribute to force the memory into M20K memory blocks.
- For direct memory instantiation, set the ram_block_type to M20K
- Use the following QSF assignment to prevent mapping from M20K memories to MLABs: “set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION OFF”
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.