Article ID: 000093108 Content Type: Troubleshooting Last Reviewed: 12/01/2023

Why do I see a high Bit Error Rate (BER) when using the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in external loopback mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Deterministic Latency PHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation of the default F-Tile PMA/FEC Direct PHY transmitter parameter setting, you will see high Bit Error Rate (BER) if the external loopback insertion loss is larger than 5 dB. The default transmitter parameters can work well only with insertion loss smaller than 5 dB.

    Resolution

    With the situation if the insertion loss is larger than 5 dB, you need to add optimal TX analog parameters in qsf file to avoid BER. Future application note will be updated to guide the debug.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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