Article ID: 000093044 Content Type: Troubleshooting Last Reviewed: 08/16/2023

Why does my Intel Agilex® 7 FPGA F-Tile A0 ES design fail to operate correctly when loaded from flash but works correctly when loaded from sof (JTAG)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 22.3, and earlier, the Intel Agilex® 7 FPGA F-Tile bit stream can be corrupted during the conversion process.

    This problem is typically seen by the F-Tile PCIe IP failing to link train correctly but can potentially impact other F-Tile functionality.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software versions 22.3 and earlier, install the respective patch below, recompile and regenerate your programming files.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs