Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you might see the following error message during the PHY Lite for Parallel Interfaces Intel® FPGA IP example design simulation with the pin width set to 4.
Error: ../../ip/ed_sim/ed_sim_mem_0/altera_phylite_agent_191/sim/phylite_agent.sv(260): (vopt-3373) Range of part-select [3:4] into 'data_out' [3:0] is reversed.
# ** Error (suppressible): ../../ip/ed_sim/ed_sim_mem_0/altera_phylite_agent_191/sim/phylite_agent.sv(260): (vopt-2957) LSB 4 of part-select into 'data_out' is out of bounds.
Currently, no workaround to this problem exists, pin widths of 4 or less show this problem. Pin widths of 5 will work.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.