Article ID: 000092966 Content Type: Error Messages Last Reviewed: 08/15/2023

Why is an error message shown when opening the PHY Lite for Parallel Interfaces Intel FPGA IP with the “Use dynamic reconfiguration” feature enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, an error message will be seen in the System Messages tab when opening the PHY Lite for Parallel Interfaces Intel FPGA IP with the “Use dynamic reconfiguration” feature enabled in the IP Parameter Editor Pro:

    Error: Factory com.altera.sopcfactories.QsysFactory reading <design directory>\phylite_s20_enable_dynamic_reconfig_example_design\phylite_debug_kit.qsys exception com.altera.utilities.altNode.AltNodeException: (in-memory string): Premature end of file. (XML)

    Resolution

    No workaround to this problem exists when using the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

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    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs