Article ID: 000092786 Content Type: Troubleshooting Last Reviewed: 12/14/2022

Why is there a removal timing violation when using P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*?

Environment

    Intel® Quartus® Prime Pro Edition
    Interfaces
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you may see a removal timing violation from "*|intel_pcie_ptile_ast_0|soft_logics|rst_ctrl|p*_reset_status_s_q" when using P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*.

Resolution

This problem is fixed in Intel® Quartus® Prime Pro Edition Software version 22.3 and onward.

Related Products

This article applies to 2 products

Intel® Stratix® 10 DX FPGA
Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

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