Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you might see this internal error when compiling the LVDS SERDES Intel® FPGA IP with the "Use external PLL" option enabled. The error occurs when another IOPLL Intel® FPGA IP is being cascaded to the external PLL.
The external PLL cannot be cascaded from another PLL as the jitter is too high.
Resolution
To avoid this error, make sure the external PLL of LVDS SERDES Intel® FPGA IP is not cascaded from another PLL.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.4 and an error message is generated.