Article ID: 000092775 Content Type: Error Messages Last Reviewed: 06/18/2024

Why do I see multiple warnings "Warning: NUMERIC_STD."=": metavalue detected, returning FALSE" when simulating the FIR II FPGA IP Core?

Environment

    Intel® Quartus® Prime Design Software
    FIR II Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

These warnings occur during simulation due to an uninitialized data counter signal driving a state machine in the FIR II FPGA IP Core generated file: auk_dspip_avalon_streaming_source_hpfir.vhd.

Resolution

These warnings are not expected to cause any functional issues as the state machine is driven to a known state during reset.

This Warning can be safely ignored by users.

This problem is not scheduled to be fixed in a future release of the Quartus® Prime Software.

Related Products

This article applies to 10 products

Cyclone® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel® MAX® 10 FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® IV FPGAs

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