Article ID: 000092684 Content Type: Product Information & Documentation Last Reviewed: 11/22/2023

What is the equation to estimate the configuration time when using Normal mode or Page mode and flash data width of 32 in the Parallel Flash Loader (PFL) Intel® FPGA IP?

Environment

    Intel® Quartus® Prime Pro Edition
    Parallel Flash Loader Intel® FPGA IP
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Description

Use the following equations when using Normal mode or Page mode and a flash data width of 32 in the Parallel Flash Loader Intel® FPGA IP. 

 

Resolution

Cflash=Caccess/4

The other equations are the same as the equations for the flash data width of 16 shown in Table 19.  FPP and PS Mode Equations for the parallel flash loader (PFL) of the Parallel Flash Loader Intel® FPGA IP User Guide.

Related Products

This article applies to 5 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Arria®
Intel® Cyclone®
Intel® MAX® CPLDs and FPGAs
Intel® Stratix®

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