Can DCLK toggle from high to low any time before or during nSTATUS going high when using FPP and PS configuration schemes on Intel® Cyclone® 10 LP?

In the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook Figure 102. "FPP Configuration Timing Waveform" and Figure 104. "PS Configuration Timing Waveform", there is a min time tST2CK spec for how long from nSTATUS going high until you are allowed the first rising edge on DCLK.  This states that DCLK must be low for that minimum duration (tST2CK) before nSTATUS goes high.

Prior to configuration, DCLK cannot toggle from low to high before nSTATUS is high. Once nSTATUS is high, DCLK must remain low for a minimum duration defined by the tST2CK specification.

If DCLK is already in a high state prior to nSTATUS going high, it can transition from high to low provided the tST2CK specification is met.