Article ID: 000092652 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why doesn't i_tx_pll_locked assert after enabling the AN/LT feature when using the E-Tile Ethernet IP for Intel Agilex® 7 FPGA IP?

Environment

    Intel® Quartus® Prime Pro Edition
    E-tile Hard IP for Ethernet Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IP User Guide, when you follow the external hard reset sequence with AN/LT enabled, you will see i_tx_pll_locked remains low when i_csr_rst_n=1'b0.  

Resolution

To work around this problem, release i_csr_rst_n after ninit_done without waiting for i_tx_pll_locked = 1'b1.

Related Products

This article applies to 2 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.