Article ID: 000092593 Content Type: Troubleshooting Last Reviewed: 03/24/2023

Why is there invalid data on the rx_avs interface of Serial Lite IV Intel® FPGA IP on Intel Agilex® 7 devices and Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, you might see invalid data on the rx_avs interface of Serial Lite IV Intel® FPGA IP if you reset its link partner Serial Lite IV Intel® FPGA IP.  

     

    The following is an example waveform capture for invalid data:

    1. rx_avs_data will toggle, containing some random data.
    2. rx_avs_valid will toggle, but no sop/eop asserted when rx_avs_valid is high.
    3. rx_link_up will go high with unexpected random data and valid indication. rx_error shows a PCS error.

    Resolution

    To fix this problem, download and install the following patch:

    This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs