Article ID: 000092533 Content Type: Troubleshooting Last Reviewed: 10/07/2022

Why do I see that mem_reset_n and mem_cke assertion does not meet the JEDEC specification at Intel® Arria®10 FPGA DDR4, DDR3 IP EMIF IP simulation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see the DDR4 and DDR3 initializing sequence timing violation where JEDEC specification defines 500us at simulation.

    Resolution

    This is to shorten the simulation time and the actual hardware follows the JEDEC specification. 

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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