Article ID: 000092452 Content Type: Troubleshooting Last Reviewed: 10/24/2022

Why do I see stability problems with the JESD204C design examples which use the F-Tile JESD204C Intel® FPGA IP in external loopback?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the JESD204C design examples which use the F-Tile JESD204C Intel® FPGA IP in external loopback may experience stability problems.

    Depending on the exact variant you are using, these problems might manifest themselves as emb_unlock_err, sh_unlock_err, rx_gb_underflow_err, cmd_par_err, invalid_eoemb, invalid_eomb, invalid_sync_header and lane_deskew_err events.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.3.
    Download and install patch 0.11 from the appropriate link below, then re-generate your programming file.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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