Article ID: 000092449 Content Type: Troubleshooting Last Reviewed: 10/24/2022

Why do I see stability problems with the dynamic reconfiguration design example which uses the F-Tile Ethernet Multirate Intel® FPGA IP with FGT PMAs in external loopback?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, the dynamic reconfiguration design examples which use the F-tile Ethernet Multirate Intel® FPGA IP in external loopback with FGT PMAs may experience stability problems.

    Depending on the exact multirate variant you are using, these problems might manifest themselves as packet count mismatches, PTP accuracy failures, PTP ready timeouts, PTP initialization failures, unexpected PTP status register values, RX PCS ready timeouts, RX FEC lock failures or RX packet valid timeouts.

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 22.3.
    Download and install patch 0.11 from the appropriate link below, then re-generate your programming file.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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