Article ID: 000092407 Content Type: Error Messages Last Reviewed: 04/16/2024

Why does the simulation for F-Tile Ethernet FPGA Hard IP Design Example hang when 25G Ethernet mode and RS-FEC are enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software Version 22.3, the simulation for F-Tile Ethernet FPGA Hard IP Design Example will hang when 25G Ethernet mode and RS-FEC are enabled.

    Resolution

    There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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