Article ID: 000092376 Content Type: Error Messages Last Reviewed: 09/28/2022

ID:20621 3V I/O <text> has <number> enable signals and is locked at pins <text> of the same 3V I/O set. Only two enable signals are allowed.

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier for Intel® Stratix® 10 devices, you might see this error message during compilation when only 2 in-out pins are used at 3V I/O bank.

     

    This is because the output-only pin in 3V I/O bank of Intel Stratix 10 devices will drive a strong "1" during configuration, the Intel Quartus Prime Pro Edition Software inserts an output-enable (OE) to disable this output until configuration complete.

    Resolution

    To work around this problem, do not exceed the OE limit with no more than 2 in-out or output-only pins in total in a 3V I/O bank.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

     

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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