Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier for Intel® Agilex™ devices, you might see the data is sampled on the rising edge while the design uses falling edge sampling. This problem occurs when the FAST_OUTPUT_REGISTER assignment is enabled and the falling edge of the clock is used. For Intel® Agilex™ devices, the register in the I/O cell does not support falling edge sampling.
There is no warning or error message.
To work around this problem, either use the rising edge of an inverted clock or do not implement the register in the I/O cell.
Future versions of the Intel® Quartus® Prime Pro Edition Software are scheduled to generate an error/warning message for this situation.