Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, you might see this error during elaboration using the Cadence* Xcelium* simulator version 21.09.003. The error occurs when a post-fit or post-synthesis Verilog HDL netlist file (.vo) generated by the Intel® Quartus® Prime Pro Edition Software EDA Netlist Writer is compiled as a Verilog HDL file.
Resolution
To work around this problem, compile the .vo file as a SystemVerilog HDL file by adding the -sv switch to the xmvlog command.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.