Article ID: 000092312 Content Type: Error Messages Last Reviewed: 10/04/2022

Why does the F-tile PMA/FEC Direct PHY Intel® FPGA IP design example fail at logic generation for Intel® Agilex™ devices??

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the F-Tile PMA/FEC Intel® FPGA IP for Intel® Agilex™ devices will fail during the compilation process when you enable double width with PMA width 16. The following error messages will appear during the Logic Generation stage:

    • Error(21843): Conflict 0
    • Error(21843): Rule: gdr_wrapper::topology_mapping_mux_rule @
    • Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings
    • Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577a.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
    • Error(21843): Rule:gdr_virtual_channel::topo_and_stream_down_to_maib_adapter_tx_and_rx_fifo_mode_and_width_rules@ gdr
    • Error(21843): gdr.z1577a.topology !=UX16E400GPTP_XX_DISABLED_XX_DISABLED ||gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == FALSE ||gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src !=E400G_STREAM15_SYS_CLK_SRC_XCVR ||
      gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode !=E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER ||gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode !=E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP ||
      gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use !=E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE ||gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width inside {E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32}
    • Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED
    • Error(21843): user.bb_f_ehip_tx[0] ->MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx
    • Error(21843): is_used == TRUE Error(21843): location == E400G_25G_15
    • Error(21843): sys_clk_src== SYS_CLK_SRC_XCVR
    • Error(21843): tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_REGISTER
    •  Error(21843): tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE
    • Error(21843): tx_xcvr_width == TX_XCVR_WIDTH_16

    This problem occurs because the F-Tile PMA/FEC Intel® FPGA IP does not support PMA width = 16 when in double-width mode.

    Resolution

    To work around this problem, do not generate the F-Tile PMA/FEC Intel® FPGA IP with PMA width = 16 when in double-width mode.

    For more information on supported configurations, refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

     

    This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.