Why does the O-RAN FPGA IP Design Example report Rx Frame Error 0x00000001 when running on hardware?

When running the O-RAN FPGA IP Design Example for 25G Ethernet Hard IP on hardware, errors will be seen in the system console window: 

Rx Frame Error 0x00000001

This problem occurs when the oran_agilex.tcl script is sourced without any errors, the chkphy_status command is issued, the clock frequencies are correctly set and the RX frequency is locked as expected. However, a frame error is seen.

To work around this problem, generate the Ethernet IP using the RS-FEC (528,514) instead of Firecode, recompile the design, program the FPGA with newly generated file and follow steps as mentioned in the User guide. RX frame error should not be seen with these changes.