Article ID: 000092271 Content Type: Connectivity Last Reviewed: 10/14/2022

Why does Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP fail to receive Ethernet packets when using linux-socfpga 5.15.x and u-boot-socfpga v2022.01 onwards with the Intel Stratix 10 SoC Design Example for 10Gbe?

Environment

  • Intel® Quartus® Prime Design Software
  • Intel® FPGA IP Low Latency 10-Gbps Ethernet MAC and PHY Function IP-10GEUMAC
  • u-boot-socfpga v2022.01

    Other Linux family*

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    Description

    Due to a compatibility problem between uboot-socfpga v2022.01 and the Intel Stratix 10 SoC Design Example for 10Gbe,  the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP might fail to receive Ethernet packets  when using the linux-socfpga 5.15.x kernels.

    The error is observed looking at the Rx errors counter when calling the ifconfig command from Linux shell. This problem also might affect designs targeting Intel® Agilex™  devices,  for accesss from the FPGA via the FPGA-to-HPS bridge. 

     

     

    Resolution

    This problem has been resolved for the u-boot-socfpga 2022.01 and 2022.04 branches

    • Ensure that you have the latest patches from u-boot-socfpga 2022.01  / 2022.04 branches
    • Relevant commits
      • 2022.01 - https://github.com/altera-opensource/u-boot-socfpga/commit/2544e805ea2b6e87a9261d51bb4fce10d78d1c2f
      • 2022.04 - https://github.com/altera-opensource/u-boot-socfpga/commit/fcf317324c5a9118a0d6d261f5a657a78ec31fa0

     

    For latest hardware or software version compatibility information, refer to the User Manual for Intel Stratix 10 SoC Design Example on Rocketboards.org.

    Note: The following issue might occur with the current resolution in place: How to configure FPGA-to-SDRAM interface when ECC is turned on in Intel® Stratix® 10 SX devices?

     

     

    Related Products

    This article applies to 3 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® Development Kits

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