Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see this internal error during the compilation of Intel Agilex® 7 FPGA designs that include the LVDS SERDES Intel® FPGA IP. This error occurs when the data rates for the RX and TX blocks are not the same.
Resolution
To work around this problem, change the data rates of the RX and TX blocks so they are both the same.
This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 22.3.