Article ID: 000091616 Content Type: Maintenance & Performance Last Reviewed: 09/02/2022

What could be the reason for the low write performance Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP write response path in AXI backpressure mode?

Environment

  • Intel® Quartus® Prime Design Software
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The low write performance on write response path in AXI backpressure mode is due to the following reason:

    When AXI backpressure is enabled, the desirable write throughput numbers cannot be achieved.  In this mode, a soft-logic read response FIFO is instantiated, but it is currently too shallow to absorb bursts of write responses resulting in the Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP being backpressured. Internal to the HBMC, this backpressure results in backpressure on the write command channels, which is what limits the overall system throughput.

     

     

    Resolution

    The depth of the write response Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP FIFO needs to be increased from 16 to 32. Because 12 FIFO slots are needed to adapt the AXI4 and HBMC backpressure protocols, the number of slots available for buffering increases from 4 to 28. The number of MLABs is unchanged, but the FIFO counter width increases by 1 bit. 

    This problem is currently scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA

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