Why is my calculated value for Tx or Rx UI incorrect when using the scripts found in the design examples for Precision Time Protocol (PTP) variants of the F-Tile Ethernet Intel® FPGA Hard IP?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the scripts provided in the F-Tile Ethernet Intel® FPGA Hard IP Designs with Precision Time Protocol (PTP) can show incorrect Tx or Rx UI values.

To work around  this problem,  perform the following steps:

1. Open the PTP firmware script located at <generated example design folder>/hardware_test_design/hwtest/altera/ptp/ptp_fw.tcl
2. Find and replace the following lines of code:

• FROM set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x3FFF0000] >> 16]]
• TO set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x7FFF0000] >> 16]]

• FROM set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x3FFF0000] >> 16]]
• TO set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x7FFF0000] >> 16]

• FROM set tx_tam_cnt_delta_max 32767
• TO set tx_tam_cnt_delta_max 32768

• FROM set rx_tam_cnt_delta_max 32767
• TO set rx_tam_cnt_delta_max 32768

6. ​​​​​​​Save the file 

This problem has been fixed starting in version 22.3 of the Intel® Quartus® Prime Pro Edition Software.