Article ID: 000091610 Content Type: Errata Last Reviewed: 01/11/2023

Why is my calculated value for Tx or Rx UI incorrect when using the scripts found in the design examples for Precision Time Protocol (PTP) variants of the F-Tile Ethernet Intel® FPGA Hard IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the scripts provided in the F-Tile Ethernet Intel® FPGA Hard IP Designs with Precision Time Protocol (PTP) can show incorrect Tx or Rx UI values.

    Resolution

    To work around  this problem,  perform the following steps:

    1. Open the PTP firmware script located at <generated example design folder>/hardware_test_design/hwtest/altera/ptp/ptp_fw.tcl
    2. Find and replace the following lines of code:
    • FROM set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x3FFF0000] >> 16]]
    • TO set tx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x7FFF0000] >> 16]]
    1.  
    • FROM set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x3FFF0000] >> 16]]
    • TO set rx_tam_cnt [format 0x%X [expr [expr $rd_data & 0x7FFF0000] >> 16]
    1.  
    • ​​​​​​​FROM set tx_tam_cnt_delta_max 32767
    • TO set tx_tam_cnt_delta_max 32768
    1.  
    • FROM set rx_tam_cnt_delta_max 32767
    • TO set rx_tam_cnt_delta_max 32768
    1. ​​​​​​​​​​​​​​Save the file 

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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