Article ID: 000091595 Content Type: Error Messages Last Reviewed: 09/02/2022

Why is the F-Tile JESD204C Intel® Agilex™ FPGA IP Design Example simulation failing with signal rx_gb_underflow_err being asserted?

Environment

  • Intel® Quartus® Prime Pro Edition
  • ModelSim*-Intel® FPGA Edition Software
  • Questa*-Intel® FPGA Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Modelsim* Intel® FPGA Edition 2021.4 and Questa* Intel® FPGA Edition 2022.1, a variation in rx_phy_clk frequency leads to the signal rx_gb_underflow_err being asserted.
    This problem is observed only in the following variant:
    L = 16, M = 8, F = 2, DATA RATE/L = 32000.000000Mbps, FCLK_MULP = 1, WIDTH_MULP = 4

     

     

     

    Resolution

    This problem impacts Intel® Quartus® Prime Edition Software IP versions 22.2 and onward. To work around this problem:

    For Modelsim*, run the simulation using v2022.1 instead of v2021.4.
    For Questa*, run the simulation using v2021.3 instead of v2022.1.

    This problem is scheduled to be fixed in a future release of Modelsim* Intel® FPGA Edition and Questa* Intel® FPGA Edition. 

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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