Article ID: 000091532 Content Type: Errata Last Reviewed: 01/11/2023

Why does the F-tile Ethernet Multirate Intel® FPGA IP have hold time violations on it’s i_reconfig_clk domain?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the F-tile Ethernet Multirate Intel® FPGA IP can have hold time violations on its i_reconfig_clk domain.

    These hold violations as shown in the Synopsys Design Constraint (.sdc) timing reports are typically seen with a “To Node” path containing “pld_avmm2_clk_rowclk.reg”  and are similar to the following format:
    eth_f_dr_top_wrapper_auto_tiles|z1577a_x0_y0_n0|avmm2_21~maib_ss_lib/x0/u23_2/pld_avmm2_clk_rowclk.reg

    Resolution

    To work around this problem, compile the design with multiple seeds until a passing seed is found.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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