Article ID: 000091513 Content Type: Product Information & Documentation Last Reviewed: 07/19/2022

What are the correct register settings for transceiver reconfiguration controller tap 5 offset of dfe_offset register for Stratix® V and Arria® V FPGAs?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Transceiver Reconfiguration Controller DFE registers information for address 0x1B (dfe_offset), offest 0x5 (tap 5) is not correct in the V-Series Transceiver PHY IP Core User Guide.

Resolution

The correct settings for tap 5 coefficients and polarity are as follows:

OffsetBitsR/WRegister NameDescription
0x5[2]RWtap 5 polarity

Specifies the polarity of the fifth post tap as follows:

  • 0: negative polarity
  • 1: positive polarity
[1:0]RWtap 5Specifies the coefficient for the fifth post tap. The valid range is 0–3.

The V-Series Transceiver PHY IP Core User Guide is scheduled to be updated in a future release.

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs

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