Article ID: 000091477 Content Type: Error Messages Last Reviewed: 09/12/2023

Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example fail in compilation?

Environment

  • Intel® Quartus® Prime Design Software
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example generated using preset 10GBase-R Example Design fails to compile with the error message as shown below.

    Error: Error opening /alt_em10g32_0_EXAMPLE_DESIGN/LL10G_10GBASER/rtl/address_dec/ip/address_dec/address_dec_merlin_mstr_trans_0.ip. 
     

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3.

    Related Products

    This article applies to 5 products

    Arria® V FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Stratix® V FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs

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