Article ID: 000091457 Content Type: Errata Last Reviewed: 07/07/2022

Why does the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to receive VirtIO Transaction Level Packets?

Environment

  • Intel® Quartus® Prime Pro Edition
  • OS Independent family

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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the address decoding of the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* may fail when receiving a VirtIO Transaction Level Packet (TLP), causing the TLP to be ignored.   
     

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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